The present invention relates to a process for the production of a semiconductor device, and more specifically to a process for the production of a semiconductor device having a structure in which one gate electrode is formed above a channel-forming region and the other gate electrode is formed below the channel-forming region.
It is known that complete isolation of semiconductor devices can be achieved and "soft error" and a "latch-up" phenomenon which is inherent in CMOS transistors can be prevented by the formation of a semiconductor device in a semiconductive layer formed on an insulating layer. A semiconductor device formed in a semiconductive layer (to be called an "SOI" layer for convenience hereinafter) formed on an insulting layer will be referred to as an SOI (Silicon-On-Insulator) type semiconductor device. It has been studied since a relatively earlier time whether or not high-speed performance and high reliability of a semiconductor device can be accomplished by forming an SOI type semiconductor device (for example, CMOS transistors) in an approximately 0.5 .mu.m thick SOI layer composed of, for example, silicon.
In recent years, the following has been found. The thickness of the semiconductive layer is adjusted to 100 nm or less, source/drain regions are formed in the entire region of the semiconductive layer in its thickness direction, and a portion of the semiconductive layer below a gate electrode is adjusted to have a relatively low impurity concentration, in order to bring the whole of the portion of the semiconductive layer into a depletion state. In this case, short channel effect can be suppressed, and current driving capacity of the semiconductor device can be improved. Further, high-speed performance of the semiconductor device can be achieved at a low supply voltage, so that a low power consumption can be materialized.
For example, when a MOS type field-effect transistor (to be sometimes referred to as "MOS-FET" hereinafter) is fabricated, one gate electrode is formed above a channel-forming region and the other gate electrode is formed below the channel-forming region, whereby short channel effect can be suppressed, a threshold voltage (V.sub.th) and "swing" can be controlled, and further, there can be fabricated an X-MOS (MOS-FET which permits concurrent operation of the gate electrodes formed above and below the channel-forming region).
For forming a semiconductive layer on an insulating layer, a SIMOX (Separation by IMplanted OXygen) method or a so-called substrate-bonding method are known, while these methods have their merits and demerits. That is, the SIMOX method is excellent in uniformity of the SOI layer, while it has a defect that flatness of an interface between an insulating layer and a semiconductive layer is not so good. The substrate-bonding method shows excellent flatness of an interface between an insulating layer and a semiconductive layer, while it has a defect that it is difficult to form a uniform semiconductive layer having a particularly thin thickness.
The method of producing a semiconductor device structured to have gate electrodes formed above and below a channel-forming region according to a conventional substrate-bonding method will be explained with reference to FIGS. 12A, 12B, 13A, 13B, 14A, 14B and 15 hereinafter. FIGS. 12A, 12B, 13A, 13B, 14A, 14B and 15 show schematic partial cross-sectional views of a silicon semiconductor substrate, and so forth when the silicon semiconductor substrate, and so forth are cut in the length direction of a gate electrode.
[Step-10]
First, a convex portion 10A is formed in a semiconductor substrate 10 composed of a silicon semiconductor substrate by lithography and etching processes. Then, an approximately 50 nm thick first insulating film 121 of SiO.sub.2 is formed on the entire surface by a known thermal oxidation method. Then, a polycrystalline silicon (polysilicon) layer containing an impurity is formed on the entire surface by a known CVD method, and then, the polycrystalline silicon layer is patterned to form a first gate electrode 122 on the convex portion 10A of the semiconductor substrate 10. At the same time, a first word line 123 extending from the first gate electrode 122 is formed on the first insulating film 121. This state is shown in FIG. 12A. The first insulating film 121 formed on the surface of the convex portion 10A of the semiconductor substrate 10 also works as a first gate insulating film.
[Step-20]
An interlayer 16 is formed on the entire surface by a CVD method, and then the top surface of the interlayer 16 is planarized (see FIG. 12B). The interlayer 16 may have a two-layered structure, for example, an SiO.sub.2 film and a polycrystalline silicon film formed thereon. The semiconductor substrate 10 and a supporting substrate 17 are bonded to each other through the interlayer 16 (see FIG. 13A). For example, the bonding is carried out under a condition of an oxygen gas atmosphere at 1100.degree. C. for 30 minutes.
[Step-30]
Then, the semiconductor substrate 10 is ground and polished from its rear surface. Specifically, for leaving no grinding damage in the semiconductive layer, first, the semiconductor substrate 10 is mechanically ground with diamond grinding grains from its rear surface until the semiconductor substrate 10 comes to have a thickness of several .mu.m on the first insulating film 121 (see FIG. 13B). Then, the semiconductor substrate 10 is selectively polished with a chemical/mechanical polishing method (CMP method) until the bottom 121A of the first insulating film 121 is exposed. The first insulating film 121 works as a polishing-stop layer, and a semiconductive layer 10B which is a remaining portion of the semiconductor substrate 10 is left as an SOI layer (see FIG. 14A).
[Step-40]
Then, a sacrificial oxide layer is formed on the surface of the semiconductive layer 10B by a thermal oxidation method, an ion-implanting mask is formed from a resist material, and the semiconductive layer 10B is ion-implanted for threshold voltage control. Then, the sacrificial oxide layer is removed with hydrofluoric acid. This state is shown in FIG. 14B.
[Step-50]
Then, a second insulating film i.e., a (second gate insulating film 124) is formed on the surface of the semiconductive layer 10B by a thermal oxidation method. Then, a polycrystalline silicon layer containing an impurity is formed on the entire surface by a known CVD method, and the polycrystalline silicon layer is patterned to form a second gate electrode 125 on the semiconductive layer 10B through the second gate insulating film 124. At the same time, a second word line 126 extending from the second gate electrode 125 is formed on the first insulating film 121. This state is shown in FIG. 15.
In the above-produced semiconductor device, an integration degree thereof can be more significantly improved since it has a structure in which semiconductor device elements are formed below the semiconductive layer 10B, and the thickness of the semiconductive layer 10B can be determined with a relatively high degree of freedom since the thickness of the semiconductive layer 10B can be defined by the height of the convex portion 10A formed in the semiconductor substrate 10.
In the semiconductor device produced according to the above steps, the first word line 123 which is an extending portion from the first gate electrode 122 and the second word line 126 which is an extending portion from the second gate electrode 125 face each other through the first insulating film 121. Generally, the first insulating film 121 has a thickness t.sub.0 (see FIG. 14A) of approximately 50 nm when it is formed. In [step-40], the sacrificial oxide layer is formed on the surface of the semiconductive layer 10B, and after ion implantation is carried out, the sacrificial oxide layer is removed with hydrofluoric acid. As a result, the thickness t.sub.1 (see FIG. 14B) of the first insulating film 121 is decreased to approximately 10 nm.
With the above decrease in the thickness of the first insulating film 121, there is caused a problem that parasitic capacitance in a portion where the first word line 123 and the second word line 126 face each other increases, so that operation speed of the semiconductor device decreases.
In the production of the above semiconductor device, the convex portion 10A is formed in the semiconductor substrate 10 in [Step-10]. There is another method in which an oxide layer is formed on a surface region of a silicon semiconductor substrate by a selective oxidation method (LOCOS method), then, a region of a silicon semiconductor substrate surrounded by the oxide layer is left by a substrate-bonding method, as a semiconductive layer. In this method, the oxide layer is formed as one having a large thickness by a selective oxidation method. However, there is a problem that a critical dimension loss is large when the above oxide layer is formed. Further, there is another problem that the eventual semiconductive layer is liable to have defects since the semiconductive layer has a stress due to the formation of the oxide layer. The SOI type semiconductor device is being employed for LSIs of a next generation and generations thereafter, while it is a serious problem that the critical dimension loss is large. Further, thickness of the semiconductive layer is determined depending upon the thickness of the oxide layer, and it is difficult in many cases to form a semiconductive layer having a thin thickness.